1. Field of the Invention
The present invention relates to a manufacturing process of semiconductor device, and, more particularly, to a manufacturing process of semiconductor device having a multi-level wiring structure.
2. Description of the Related Art
As an integrated circuit is integrated in higher and higher density, it is essential to employ multi-level wiring in constituting a semiconductor device. A silicon oxide type dielectric film is frequently used for an inter-level dielectric film of a semiconductor device with multi-level wiring to reduce parasitic capacitance between wiring. A silicon oxide film formed by a plasma chemical vapor deposition is widely used as an inter-level dielectric film for aluminum type wiring because it can be formed at a relatively low temperature of 500.degree. C. or less, and has good film quality. Description is given in the following on a process for forming a multi-level wiring structure presented by B. M. Somero et al. on the VLSI Multilevel Interconnection Conference, 1993.
As shown in FIG. 9(a), underlying wiring is formed on a semiconductor substrate 201. The wiring has a multi-level structure. First, a first titanium film 202 and a first titanium nitride film 203 are continuously formed in a same processing chamber. The titanium film and the titanium nitride film are used for improving migration resistance characteristics of the wiring. Then, a copper containing aluminum film 204 and a second titanium nitride film 205 are formed by a sputtering process. Containing copper in the aluminum film is also aimed at improving migration resistance characteristics. The top titanium nitride film 205 is used for preventing optical reflection since a desired pattern cannot be obtained if light is reflected on an aluminum film during exposure in a photolithography process for forming wiring.
After the underlying wiring is formed, as shown in FIG. 9(b), a plasma silicon oxide film 206 is formed by a parallel-plate type plasma chemical vapor deposition using tetraethylorthosilicate and oxygen as materials.
Since the surface of plasma silicon oxide film 206 is non-planar reflecting the profile of underlying wiring, if the upper level wiring is formed as it is, reliability of the wiring is deteriorated due to physical breakdown (disconnection) of the wiring. Therefore, to obtain good planarity, this example comprises applying photoresist on the plasma silicon oxide film 206, and heat treating it, followed by etch back to obtain the profile of FIG. 9(c). Although the conventional process employs the above approach, it may employ other approaches such as a spin-on-glass film or chemical mechanical polishing.
After the surface of the first silicon oxide film is planarised, contact holes (via holes) 209 are formed for electrically connecting the underlying wiring by photolithography, whereby the structure shown in FIG. 9(d) is obtained. In opening a via hole, the second titanium nitride film 205 on the top of underlying wiring is also etched to reduce contact resistance so that the first copper containing aluminum film 204 is exposed to the bottom of via hole.
Then, as shown in FIG. 10(a), a second titanium film 210 and a third titanium nitride film 211 are formed with a sputtering process. The second titanium film 210 is essential to reduce contact resistance at the bottom of via hole. Since aluminum is very easily oxidized, via hole resistance increases if aluminum oxide is formed on the copper containing aluminum wiring at the bottom of the via hole. On the other hand, titanium exhibits strong reduction (deoxidizing) characteristics. Accordingly, when a thin titanium film is formed, the titanium reduces aluminum oxide, so that increase of resistance is suppressed. Oxide of titanium also has high resistance, but, unlike aluminum, is not formed all over the bottom of via hole, but aggregates on one area, so that there is no increase of resistance.
The third titanium nitride film 211 is used for preventing a subsequently formed tungsten film from being peeled off, and as a stopper layer in a case where the global etch back is performed after the tungsten film is formed. If the tungsten film is directly formed on the titanium film 210, the tungsten film may be peeled off. In addition, since there is a large difference in the etching rate between titanium nitride and tungsten during dry etching, it becomes possible to etch tungsten without leaving it on areas other than the via hole when the etch back is performed to leave tungsten only in the inside of via hole.
Then, the via hole 209 is filled with tungsten 212 to obtain a structure shown in FIG. 10(b). The structure shown in FIG. 10(b) can be obtained by first forming tungsten on the entire surface of a wafer by chemical vapor deposition, and leaving the tungsten only in the inside of via hole 209 by etching back the entire surface.
Subsequently, similar to the underlying wiring, a second copper containing aluminum film and a fourth titanium nitride film are formed by sputtering, then a desired wiring pattern is formed, thereby a multi-level wiring structure as shown in FIG. 10(c) can be obtained.
However, according to this approach, a void 207 is generated in the underlying wiring of the plasma silicon oxide film 208 as spacing between the wirings become narrow This is caused from the fact that the film formation rate of the plasma oxide silicon film is higher at the upper corner of the wiring than on the side wall of the wiring or the valley between the wiring. If a void is caused between the wiring, gas contained in the void is repeatedly expanded and contracted in heating and cooling in the subsequent steps. Since the inter-level dielectric film does not have flexibility enough to absorb such expansion or contraction of the volume of gas in the void, such force would be applied to the wiring. If a large force is applied to the wiring during heating and cooling, the reliability of the wiring deteriorates significantly due to stress migration or the like. Accordingly, it is necessary to have a technique for forming an inter-level dielectric film so that no void is generated between the wiring.
The process not to generate the void includes a high density plasma CVD process which forms a film while applying high frequency power to a substrate. This process performs sputter etching at the same time while the film is formed. In the sputter etching, the upper comer of the wiring is more effectively etched than at other areas. Consequently, the upper comer of the wiring has a lower film formation speed so that the void does not tend to be generated between the wiring.
Since this process performs etching at the same time as the film formation, the film formation speed would be lowered. Thus, it is a typical approach to effectively decompose the film forming material by generating high density plasma, thereby increasing the film formation speed (high density plasma CVD process). In the following, a process for forming a film with the high density plasma CVD process while applying bias to the substrate is simply called a high density plasma CVD process.
The high density plasma CVD process includes an ECR plasma CVD process using electron cyclotron resonance which was reported by S. E. Lassig et al. on the VLSI Multilevel Interconnection Conference, 1993; a helicon plasma CVID plasma using helicon wave which was reported by T. Tamura et al. on the Dielectric for VLSI/ULSI Multilevel Interconnection Conference, 1995; and an ICP-CVD process using inductively coupled plasma which was reported by W. van den Hoek et al. on the SEMI Technology Seminar, 1994.
When the inter-level dielectric film is formed by the high density plasma CVD process, it is possible to obtain a multi-level wiring structure free from a void in the silicon oxide film even in a narrow wiring spacing as shown in FIG. 11. However, this process has various problems.
When the inter-level dielectric film formed by the high density plasma CVD process is used for the multi-level wiring structure described in conjunction with the related art, the reliability is degraded for a contact hole (via hole) electrically connecting an upper wiring and an underlying wiring.
It is because the silicon oxide film of the high density plasma CVD used as the inter-level dielectric film contains much amount of hydrogen, and the hydrogen is out-diffused and desorbed after the multi-level wiring structure is formed.
A dual-level wiring structure shown in FIG. 11 was formed by using a silicon oxide film, which was formed by the high density plasma CVD process described in conjunction with the related art, as an inter-level dielectric film. Then, its via hole-electrical resistance characteristics were evaluated by the following method.
To evaluate the reliability of the structure shown in FIG. 11 after it was formed, via hole resistance immediately after formation of a via hole was measured. Then, heat treatment (raised temperature test) was conducted for 60 minutes at 450.degree. C. in nitrogen atmosphere, for 60 minutes at 500.degree. C., 10 hours at 500.degree. C. in this order. The via hole resistance was measured every time. The via holes were arranged in a chain of 2000 holes. The represented resistance was the value per hole. As shown in FIG. 12, after the raised temperature test was conducted in nitrogen atmosphere at 500.degree. C. for 10 hours, the via bole resistance increased by about 22 times in comparison with that before the raised temperature test. The reason appears to lie in the following.
First, to determine change of the inter-level dielectric film during the heat treatment, a silicon oxide film was formed on a silicon substrate in a thickness of 600 nm by the ICP-CVD process which was one of the high density plasma CVD process, and then, a Theremal Desorption Spectrum analysis (TDS method) was conducted. A six-inch silicon substrate was used for film formation. The film was formed by using monosilane, oxygen and argon at flow rate 30 sccm, 40 sccm and 30 sccm, respectively. High frequency wave of a frequency of 2.0 MHz and with power of 3000 V was applied to a plasma source so as to generate high density plasma. In addition, high frequency bias current was applied to the substrate so as to generate self-bias. The bias frequency at the moment was 1.8 MHz, and the power was 1500 W.
As seen from theTDS shown in FIG. 13, an element with mass number of 2, i.e. hydrogen was desorbed in a much amount. The desorption of hydrogen caused a peak at 400.degree. C. or less. Accordingly, it is believed that the silicon oxide film formed by the high density plasma CVD process contains much hydrogen, and much amount of hydrogen is desorbed during the raised temperature test. The hydrogen appears to be taken into the silicon oxide film during the high density plasma CVD. That is, in the high density plasma CVD process, high RF power is applied to the substrate during film formation. This applies high self-bias on the substrate. The self-bias is applied in such a manner that the substrate is negatively charged with respect to the plasma. Since hydrogen ion generated through decomposition of the film material SiH.sub.4 is a positive ion, it is strongly attracted toward the substrate, whereby much ion is taken into the silicon oxide film.
It is known that, when hydrogen reacts with titanium, volatile TiH.sub.x is generated. Accordingly, if a semiconductor device has a structure where an inter-level dielectric film contacts titanium, there is a possibility of risk that, when much hydrogen is generated, titanium becomes fragile around the boundary between them.
In addition, when reliability is measured for the multi-level wiring structure shown in FIG. 12, warp was measured for wafers before and after the raised temperature test. As shown in FIG. 14, the warp is significantly varied before and after the raised temperature test. The warp of wafer was about 27 .mu.m before the raised test, while it was about 16 .mu.m immediately after the raised temperature test was conducted in nitrogen environment at 450.degree. C. for 60 minutes. The warping was reduced by about 11 .mu.m. Furthermore, the warp of wafer was about 4 .mu.m after the raised temperature test at 500.degree. C. for 10 hours, which showed reduction of about 23 .mu.m compared with that before the test. It is believed that, as described above, when the heat treatment is conducted, much hydrogen is desorbed from the silicon oxide film formed by the high density plasma CVD process. On the other hand, the reason why the warp increases when the wafer is left after the raised temperature test believingly lies in that water in the atmosphere where the wafer is left is absorbed to bonds which are broken when hydrogen desorbed, thereby the warp being released. Accordingly, it can be seen that warp of a wafer is significantly varied by conducting the raised temperature test, and very high force is applied to the via hole.
After the via hole resistance was measured after the raised temperature test at 500.degree. C. for 10 hours, the cross section of the via hole was observed with a scanning electron microscope (SEM). It was found that, as shown in FIG. 15, although the bottom of via hole was not peeled off from the underlying layer when compared with the state before the raised temperature test (FIG. 11), the bottom of via hole which should exist below an anti-reflection coating of the underlying wiring existed above the anti-reflection coating. This is believingly caused by the fact that mechanical force is applied to the via hole when the raised temperature test is conducted at 500.degree. C., so that the bottom of via hole is raised. Since the measurement pattern consists of a chain of 2000 via holes, it is difficult to confirm all the via holes. Accordingly, it is expected that, while there is no broken wire at the area where the observation is conducted, there are via holes exhibiting high resistance due to partial peeling.
In view of the above results, the reason why the via hole resistance is significantly varied when a wafer is maintained at a high temperature for an extended period of time is believed to lie in the fact that titanium becomes fragile within a via hole as excess hydrogen is desorbed from the high density plasma CVD silicon oxide film, thereby deteriorating adherence at the interface between the bottom of via hole and aluminum wiring. Further, as large force is applied to the via hole due to the warping of the wafer being significantly varied during heat treatment, the bottom of via hole is cause to raise from the underlying wiring, so that the via hole resistance is increased. When the silicon oxide film is formed with the high density plasma CVD process, it is unavoidable that excess hydrogen is contained in the film, as described above. Therefore, when the silicon oxide film formed by the high density plasma CVD process is used as the inter-level dielectric film, it is expected to be effective that hydrogen in the film is previously removed after formation of the film.